The present invention relates in general to data processor systems, and more particularly, to a method and apparatus for managing cycle steals in a data processor system.
In data processor systems having multiple processors, devices must be employed to allocate cycle resources between processors. A resource manager performing this function by allocating cycle resources to a data processor can easily track some of these cycle resources. Cycles used for code execution, data direct memory access (DMA) cycle steals (cycles unavailable to the data processor because of competition for a common resource), and other hardware services are easily tracked and accounted for because they are either periodic or predictable. However, cycles stolen because of asynchronous accesses to cycle resources by a second processor (such as a host personal computer) are not as easily tracked or managed.
Traditionally, the cycles stolen by the second processor have been limited by having the second processor pace itself through software timing loops in which it is assumed that each access to the data processor xe2x80x9cstealsxe2x80x9d a constant number of cycles. This approach provides a crude method of estimating the worst case cycle steal threshold. As a consequence, reduced data throughput, and unused cycle resources result. Moreover, because the software timing loops are usually based on the second processor""s system clock, typically a host processor""s system clock which is different from the data processor system clock, the host""s software is often required to perform a calibration step in order to adjust the timing loop counts.
Therefore, there is a need in the art for circuitry and methods that allow the second processor to precisely and deterministically limit and track all cycles stolen from the data processor core. Such circuitry and methods would provide a device for obtaining the maximum data throughput for a given cycle resource allocation. The same circuitry and methods would also eliminate the necessity for the software running on the second processor to perform a calibration to adjust the software timing loop counts.
The previously mentioned needs are fulfilled by the present invention. The invention tracks and deterministically limits all cycles stolen from the data processor over periods of time in which data processor resources are accessed by other processors. The invention accomplishes this by employing a cycle steal pacing counter which accumulates clock cycles during time intervals in which the data processor is being held, that is, instruction execution by the data processor stopped, because of system memory access by another processor. All such clock cycles are accumulated by the cycle steal pacing counter during a time interval corresponding to the period of an interrupt clock which is the basis for scheduling data processor tasks.
Access to data processor cycle resources is controlled by the value of the number of stolen clock cycles contained in the cycle steal pacing counter. In the time interval determined by the period of the interrupt clock, the processor seeking access to data processor cycle resources can access the cycle count value contained in the cycle steal pacing counter. This value is then used by the software controlling the access-seeking processor to limit the access to data processor cycle resources. Access limitation using software running on the accessing processor is a feature of the present invention.
The use of software in managing cycle resource accesses adds to the versatility of the invention. The algorithm controlling access to data processor cycle resources, a pacing algorithm, can be defined to best meet the needs of the data system design. During a period of time in which cycle steals by the accessing processor are inhibited because its allocation has been reached, the software can perform other activities. In contrast, a xe2x80x9chardware onlyxe2x80x9d solution would stall the accessing processor, not allowing any background processing in the accessing processor. Thus, the present invention is advantageous over the use of hardware alone to do the access pacing.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.